Job Description
You will define verification specification according to design specification and verification plan.
You will create and maintain UVM test environments.
You will also implement and execute debug test cases.
Competence/Experience – Mandatory
Experience from working with IC design/verification
Experience from verification of complex ASICs
Experience from working with UVM and System Verilog
English (verbal & writing)
Competence/Experience – ... Visa mer
Job Description
You will define verification specification according to design specification and verification plan.
You will create and maintain UVM test environments.
You will also implement and execute debug test cases.
Competence/Experience – Mandatory
Experience from working with IC design/verification
Experience from verification of complex ASICs
Experience from working with UVM and System Verilog
English (verbal & writing)
Competence/Experience – Optional
Experience from working with SpecMan
Experience from working with networking IC development/verification
Experience from creating and maintaining UVM test environment
Swedish (verbal and writing)
Personality
Strong feeling for producing high quality work
Ability to work independently
Ability to work in teams
Communication
Visa mindre